Scenario Modeler
Explore geopolitical futures and their impact on technology value chains. Select a scenario to analyse sector-by-sector exposure and cascade effects.
Taiwan Strait Advanced Logic & Packaging Shock
Taiwan blockade, quarantine, or kinetic escalation disrupts leading-edge wafer output, CoWoS packaging, shipping, and insurance
Taiwan blockade, quarantine, or kinetic escalation disrupts leading-edge wafer output, CoWoS packaging, shipping, and insurance
€2398B
Critical exposure lens x1.80
Foundry allocation freezes on leading-edge logic; orders shift to long lead-time qualified alternates.
Rank revenue-critical products by Taiwan wafer, packaging, HBM, substrate, and shipping dependency. Treat industrial automation, controls, and power-electronics suppliers as the first ask.
Fund redesigns that can run on qualified mature-node or non-Taiwan packaged alternatives where performance allows.
Persistent Taiwan route insurance repricing, quarantine language, or TSMC allocation restrictions.
Taiwan logistics and fab output constrained -> advanced logic and packaging allocation freezes
AI accelerators, premium electronics, and connected industrial products miss production windows
Governments ration strategic supply -> accelerated allied fabs, stockpiles, and redesign mandates
- PLA blockade rehearsal activity, quarantine language, or persistent grey-zone maritime disruption
- Shipping, air-cargo, and political-risk insurance repricing around Taiwan routes
- TSMC customer allocation commentary and advanced-packaging lead-time changes
- US, Japan, and EU emergency semiconductor-stockpile or export-priority measures
- Separate product exposure into wafer, packaging, HBM, substrate, and logistics dependencies
- Qualify mature-node fallbacks for control systems and non-performance-critical functions
- Pre-negotiate allocation rights for strategic SKUs and service-level exceptions
- Build redesign pathways that reduce leading-edge and Taiwan-packaging dependency over 12-24 months
TSMC reported that 7nm-and-below technologies remained the majority of wafer revenue in 2025, with 2nm entering high-volume manufacturing in Q4 2025.
Taiwan concentration remains most acute exactly where AI, HPC, and premium electronics demand is growing.
Recent AI-chip supply-chain work identifies CoWoS advanced packaging and HBM, not only logic dies, as binding accelerator constraints.
Scenario impact should model packaging and memory integration, not just foundry wafer starts.
This is one read on one moment. The drift moves weekly — the Tuesday briefing tracks it.